The present invention relates to an electrically erasable and programmable semiconductor memory device and a memory system, and more particularly a semiconductor memory device which stores multi-value data and a memory system which incorporates this semiconductor memory device.
Known as one type of an electrically erasable and programmable read-only memory (EEPROM) which can store a great amount of data is a multi-value data memory EEPROM. In the multi-value data memory EEPROM, each memory cell stores a data item having one of n values (n.gtoreq.3).
Recently, the demand for EEPROMs has been increasing, because EEPROMs hold data even after they are switched off. A flash memory is a nonvolatile semiconductor memory from which data can be erased at once. Each memory cell of the flash memory suffices to have only one transistors, unlike byte-type nonvolatile semiconductor memory in which each memory cell has the two-transistor. The cells of the flash memory can therefore be small. It follows that a flash memory can have a memory capacity and can therefore be used in replace of a magnetic disk which has a great memory capacity.
Of various types of flash memories, the NAND-type EEPROM is considered most advantageous in terms of integration density. A NAND-type EEPROM comprises a plurality of memory cells arranged in, for example, columns. Each memory cell is of n-channel FETMOS structure, having a floating gate (i.e., charge-storage layer) and a control gate. The memory cells forming a one column are connected, each with its source connected to the drain of the next memory cell. The memory cells thus connected in series constitute a unit cell-group, or a NAND cell. Hence, the NAND-type EEPROM has a plurality of NAND cells. The NAND cells are connected to bit lines.
FIG. 1A is a plan view of a NAND cell, and FIG. 1B is a circuit diagram thereof. FIGS. 2A and 2B are sectional view of NAND cell shown in FIGS. 1A and 1B. FIG. 2A is a sectional view, taken along line 2A--2A in FIG. 1A. FIG. 2B is a sectional view, taken along line 2B--2B in FIG. 1A.
An element region is provided in a p-type substrate 11 (or in a p-type well formed in an n-type substrate). An element isolation oxide film 12 surrounds the element region. Provided in the element region is a NAND cell which is constituted by eight memory cells M1 to M8 connected in series. The cells M1 to M8 have an n-channel FETMOS structure. As best shown in FIG. 2B, each cell comprises a first gate insulating film 13, floating gates 14 (14-1, 14-2, . . . , 14-8), a second gate insulting film 15, and control gates 16 (16-1, 16-2, . . . , 16-8). The first gate insulating film 13 is provided on the p-type silicon substrate 11. The floating gate 14 is mounted on the insulating film 13. The second gate insulating film 15 is provided in the floating gate 14. The control gate 16 is provided on the insulating film 15. Each of n-type diffusion layers 19 in an n-channel FETMOS structure serves as the source of one memory cell and also as the drain of the adjacent memory cell. The memory cells M1 to M8 are thereby connected in series, constituting the NAND cell.
The NAND gate thus constituted has select gates 14-9 and 16-9 at the drain side and select gates 14-10 and 16-10 at the source side. The select gates 14-9, 16-9, 14-10 and 16-10 have been formed by the same process as the floating gates 14-1 to 14-8 and control gates 16-1 to 16-8 of the memory cells M1 to M8. The select gates 14-9 and 16-9 are electrically connected at desired portions. Similarly, the select gates 14-10 and 16-10 are electrically connected at desired portions. An interlayer-insulating film 17 covers the top of the p-type silicon substrate 11 in which the NAND cell is provided. Formed on the interlayer-insulating film 17 is a bit line 18. The bit line 18 contacts the n-type diffusion layer 19 which is located at the drain side of the NAND cell. Thus, the NAND cell has its drain connected to the bit line 18 by the select gates 14-10 and 16-10.
An NAND-type EEPROM comprises many identical NAND cells of the type shown in FIGS. 1A and 1B, arranged side by side. Those memory cells of the NAND cells which form a row have their control gates 14 commonly connected, forming control gate lines. The control gate lines CG1 to CG8 are so-called "word lines" which extend in the row direction. That is, the control gate 14 of each memory cell is connected to one word line. In each NAND cell, the select gates 14-9 and 16-9 form a select gate line SG1, and the select gates 14-10 and 16-10 form a select gate line SG2. The select gate lines SG1 and SG2 extend in the row direction.
FIG. 3 is a circuit diagram illustrating a NAND-cell array. As FIG. 3 shows, control gate lines CG1 to CG8 and select gate lines SG1 and SG2 extend in the row direction. As in most NAND-type EEPROMs, the memory cells M which are connected by one control gate line (i.e., word line) form one page, and the pages located between a drain-side select gate line (i.e., select gates 14-9 and 16-9) and a source-side select gate (i.e., select gates 14-10 and 16-10) form what is generally known as "NAND block" or "block." One page contains, for example, 256 bytes having (256.times.8) memory cells. The memory cells of each page are programmed, almost at the same time. One block contains, for example, 2048 bytes, having (2048.times.8) memory cells. Data is erased from the memory cells of each block, almost at the same time.
An operation of a NAND-type EEPROM having the NAND-cell array shown in FIG. 3 will be explained. In each NAND cell, data is written first into the memory cell which is the furthest from a bit line, then into the memory cell which is the second furthest therefrom, and so forth. More precisely, a write voltage Vpp (=about 20V) is applied to the control gate of any memory cell selected, while an intermediate potential (=about 10V) is applied to the control gates of the memory cells not selected and also to the first select gate. 0V (i.e., "0" programming voltage) or the intermediate potential (i.e., "1" programming voltage) is applied to the bit line. The potential of the bit line is thereby applied to the selected memory cell. Thus, when write data is "0," a high voltage is applied between the p-type substrate and the floating gate of the selected memory cell. In this case, electrons are injected from the p-type substrate into the floating gate by virtue of tunnel effect, and the threshold voltage of the transistor of the cell increases. The threshold voltage of the transistor does not change at all when the write data is "1."
As indicated above, data is erased from the memory cells of each block, almost at the same time. All control gates and all select gates provided in the block from which to erase data are set at 0V, and a voltage VppE (=about 20V) is applied to the p-type substrate and the p-type well provided in an n-type substrate. At the same time, the voltage VppE is also applied to the control gates and select gates provided in the blocks from which to erase no data. In each memory cell incorporated in the block from which to erase data, electrons are released from the floating gate. These electrons are injected into the p-type substrate or the p-type well provided in the n-type substrate. The threshold voltage of the transistor of the memory cells therefore decreases.
At data read operation from a memory cell, the bit line is precharged, thereafter floating the bit line. Then, the control gate of the memory cell is programmed to 0V, the control gate and select gate of any other memory cell are set at the power-supply voltage Vcc (e.g., 3V), and the source line is programmed to 0V. The data in the memory cell is read by detecting the potential of the bit line by means of a sense amplifier (not shown) to determine whether a current flows in the memory cell. More specifically, if the cell stores data "0" (that is, if the memory-cell transistor has a threshold voltage Vth less than 0V), the transistor is turned off and the bit line maintains the precharge potential. If the cell stores data "1" (that is, if the memory-cell transistor has a threshold voltage Vth more than 0V), the transistor is turned on and the bit-line potential falls from the precharge potential by value .DELTA.V. Hence, the sense amplifier can detect whichever potential the bit line has, thereby to read the data from the memory cell.
The NAND-type EEPROM described above is still inferior to a magnetic disk in view of cost effectiveness. It is much desired that the NAND-type EEPROM acquire a large memory capacity to have its per-bit cost reduced. Recently, technology of storing multi-value data has been proposed which may be applied to an electrically erasable and programmable, nonvolatile memory such as the NAND-type EEPROM. Various multi-value memory cells are known, each capable of storing a data item having one of n values (n.gtoreq.3).
How a four-value cell, for example, which can store a data item having one of four different values, operate will be explained. FIG. 4 is a diagram which represents the relation between the threshold voltage of the transistor of the four-value cell and the four data items of different values the cell can store. As can be understood from FIG. 4, the memory-cell transistor has, for example, a negative threshold voltage while the cell is storing data "1," as in the case data has been read from the cell. The memory-cell transistor has a threshold voltage of, for example, 0.5 to 0.8V while the cell is storing data "2," a threshold voltage of, for example, 1.5 to 1.8V while the cell is storing data "3," and a threshold voltage of, for example, 2.5 to 2.8V while the cell is storing data "4."
When a read voltage VCG3R is applied to the control gate of the four-value cell, the transistor of the cell is turned on or off. If the transistor is turned on, data "1" or data "2" is detected. If the transistor is turned off, data "3" or "4" is detected. Then, read voltages VCG4R and VCG2R are applied to the control gate, whereby data "1," "2," "3," or "4" is detected. The read voltages VCG2R, VCG3R and VCG4R are 0V, 1V and 2V, respectively.
In FIG. 4, VGC2V, VGC3V and VGC4V represent verify voltages, which are applied to the control gate of each memory cell in order to determine whether or not the memory cell has been sufficiently programmed. The verify voltages VGC2V, VGC3V and VGC4V are 0.5V, 1.5V and 2.5V, respectively.
FIG. 5 is a diagram explaining how a four-value cell is programmed. FIG. 6 is a diagram showing which data items are written into which memory cells constituting one page. As shown in FIG. 6, a two-bit address is assigned to each memory cell MC. More precisely, address bits A0 and A1 are assigned to the memory cell MC1, address bits A2 and A3 to the first memory cell MC2, address bits A4 and A5 to the second memory cell MC3, and so forth. In accordance with two addresses, write data supplied externally is written into each memory cell MC.
To write data into, for example, the first memory cell MC1, the address bits A0 and A1 are temporarily stored in the data circuit associated with the memory cell MC1. In accordance with these bits A0 and A1, data "1", "2", "3" or "4" is written into the memory cell MC1 as is illustrated in FIG. 5. In a similar way, data "1", "2", "3" or "4" is written into any other memory cell MC2, MC3, . . . , or MC128 in accordance with two address bits A2 and A3, A4 and A5, . . . , or A254 and A255. To write data "1" into one memory cell is to maintain the memory cell in an erased (unwritten) state.
In the data-programming described above, it takes longer to write "3" into a four-value cell than to write "2" thereinto. (Writing "2" into a four-value cell is equivalent to writing "0" into a binary cell.) It takes still longer to write "4" into a four-value cell than to write "3" thereinto. Whether a four-value cell has been sufficiently programmed to each data item "2", "3" or "4" must be checked in verify mode. Much time is required to determine whether the memory cell has been sufficiently programmed. Hence, to program the memory cells of one page almost at the same time, a considerably long time will be required to write the data, in its entirety, into all the memory cells. In short, the programming time of the NAND-type EEPROM, defined as the time required to write data into the cells of one page, is inevitably long.
How to read data from a four-value cell will be explained, with reference to FIGS. 7A and 7B.
FIG. 7A is a diagram representing the distribution of threshold voltages of a four-value cell. FIG. 7B is a flowchart for explaining the conventional method of reading data from a four-value cell.
First, a voltage Vt1 intermediate between two voltages corresponding to data values "1" and "2" is applied to the word line to which the memory cell is connected (Step A1). If the memory cell is turned on, it is known that the cell stores value "0" or "1."If the memory cell is turned off, it is determined that the cell stores value "2" or "3." Next, a voltage Vt2 is applied to the word line, thereby detecting that the memory cell stores "3" or any other value "0", "1" or "2" (Step A2). Then, a voltage Vt3 is applied to the word line, determining that the memory cell stores "0" or any other value "1", "2" or "3" (Step A3). As a result, the two-bit data (a four-value data) is read from the memory cell (Step A4) and ultimately from the NAND-type EEPROM chip.
Another conventional method of reading data from a four-value cell will be explained, with reference to FIGS. 8A and 8B. FIG. 8A is a diagram representing the distribution of threshold voltages of a four-value cell. FIG. 8B is a flowchart for explaining this conventional data-reading method.
At first, a voltage Vts1 intermediate between two voltages corresponding to data values "0" and "1" is applied to the word line to which the memory cell is connected (Step B1). If the memory cell is turned on, it is known that the cell stores value "0." If the memory cell is turned off, it is determined that the cell stores value "1", "2" or "3." Next, a voltage Vts2 is applied to the word line, thereby detecting that the memory cell stores "0" or "1", "2" or "3" (Step B2). Then, a voltage Vts3 is applied to the word line, determining that the memory cell stores "3" or any other value "0", "1" or "2" (Step B3). As a result, the two-bit data (a four-value data) is read from the memory cell (Step B4) and is ultimately output to an-external device from the NAND-type EEPROM chip.
As described above, more steps must be performed to determine the threshold voltage of each memory cell in a multi-value data storing memory than in a binary storing memory. This means that the multi-value data storing memory has a lower read speed than a binary data storing memory.
In a four-value data storing memory, for example, the voltage of a word line must be changed three times to detect the threshold voltage of any memory cell connected to the word line. The read time of the four-value data storing memory is about three times as long as that of a binary data storing memory.
In an electrically erasable and programmable, nonvolatile memory such as the NAND-type EEPROM, data may be lost as electrons leak from the floating gate (i.e., a charge-storage layer) of each memory cell. Lost of data is likely to occur, particularly in multi-value data storing semiconductor memories. When data corresponding to a high threshold level is written into a memory cell, the charge in the floating gate of the cell most likely leaks, in an increasing amount, into the substrate because a strong electric field is generated between the substrate and the floating gate. The charge thus leading from the floating gate changes the threshold voltage of the memory cell. No matter how small is the change in the threshold voltage, the data is lost in the memory cell.
Therefore, multi-value data storing semiconductor memories cannot be put to practical use unless they acquire reliability against data destruction.
As mentioned above, the conventional multi-value data storing semiconductor memories are inferior to the binary data storing memories in terms of not only read time but also programming time. Further, the memories cannot be programmed sufficiently or reliably. Consequently, the conventional multi-value data storing semiconductor memories have not ever been put to practical use.